PCB Plating Voids are unplated or inadequately plated areas within a via or plated-through-hole wall. Inspectors should not accept or reject them from appearance alone. Instead, they must evaluate the void’s location, longitudinal and circumferential extent, proximity to an internal-layer connection, remaining copper thickness, product class, and applicable specification revision.
A board may pass electrical testing while a partial void remains conductive. Therefore, buyers should require microsection evidence and a documented disposition whenever the defect may reduce long-term hole reliability.
What Are PCB Plating Voids?
PCB Plating Voids occur when copper fails to form a continuous deposit over part of the prepared hole wall.
The defect may originate during:
- Drilling
- Hole cleaning
- Desmear
- Conditioning
- Electroless copper deposition
- Direct metallization
- Electrolytic copper plating
- Intermediate rinsing or handling
A void may appear as one isolated unplated area, several disconnected areas, a narrow longitudinal skip, or a larger section that interrupts the hole barrel.
However, inspectors must distinguish a true plating void from other internal defects.
| Condition | What It Means | Main Concern |
|---|---|---|
| Plating Void | Copper does not cover part of the hole wall | Reduced conductive cross-section |
| Thin Plating | Copper remains continuous but below requirement | Thermal and electrical reliability |
| Barrel Crack | Copper deposit has fractured | Intermittent or open connection |
| Interconnect Separation | Hole copper separates from an internal land | Loss of layer connection |
| Resin Recession | Resin pulls back from the hole wall | Requires separate acceptance review |
| Hole-Wall Pull-Away | Hole plating separates from the dielectric | Adhesion and thermal reliability |
| Lamination Void | Empty area exists inside the dielectric structure | Insulation and delamination risk |
For example, a dark region beside the barrel does not automatically prove missing copper. It may show resin recession, preparation damage, contamination, or a microsection-polishing artifact.
Therefore, qualified personnel should review the original microsection at suitable magnification before assigning the defect type.
Are PCB Plating Voids Acceptable?
Some specifications permit limited plating voids under defined conditions. However, no universal statement such as “one void per hole is acceptable” applies to every PCB.
Acceptance depends on:
- IPC product class
- Performance specification
- Document revision
- Customer drawing
- Hole type
- Void dimensions
- Void location
- Remaining copper
- Number of affected holes
- End-use reliability requirement
Use the following matrix as a disposition guide, not as a replacement for the governing standard.
| Observed Condition | Recommended Action | Reason |
|---|---|---|
| Complete Skip Around The Barrel | Reject | Electrical path lacks continuity |
| Void At An Internal-Layer Connection | Reject Or Escalate | Connection reliability may be compromised |
| Barrel Crack Rather Than A Void | Reject Under The Relevant Crack Criteria | Thermal cycling can open the crack |
| Remaining Copper Below Minimum | Reject | Board fails the copper requirement |
| Voids On Opposite Sides At The Same Depth | Escalate Or Reject | Conductive cross-section may become critically small |
| Multiple Similar Voids Across A Panel | Hold The Lot | Pattern suggests a process excursion |
| Small Isolated Void Away From A Layer Interface | Compare With The Exact Standard | Acceptance may depend on class and dimensions |
| Suspected Preparation Artifact | Prepare Another Section | The first section may not show the actual condition |
| Void Found Only In A Coupon | Investigate Production Correlation | The coupon may overstate or understate board risk |
The current IPC-A-600 revision includes visual acceptance information for internal copper penetration and plating voids. Meanwhile, IPC-6012 defines rigid-board qualification and performance requirements. Buyers should identify both the applicable performance specification and revision instead of writing only “IPC compliant.”
IPC lists IPC-A-600 Revision M as the May 2025 revision. Nevertheless, customer-specific requirements may remain stricter than its baseline criteria.
Why Does The Location Of A Plating Void Matter?
Two voids with the same visible area can create very different risks.
Void In The Middle Of A Continuous Barrel
An isolated void away from an internal-layer connection may leave copper on both sides and around the remaining circumference. The exact standard may permit it if its dimensions and frequency remain within the applicable limit.
However, inspectors still need to confirm the minimum remaining PCB copper thickness.
Void At An Internal-Layer Interface
A void at the point where the barrel connects with an internal pad creates greater risk. It can reduce or eliminate the electrical and mechanical connection to that layer.
Moreover, an electrical test may miss the problem if another conductive path still connects the tested nodes.
Void Near The Hole Knee
The knee is the transition between the outer land and hole wall. It can experience mechanical and thermal stress during soldering. Therefore, a void, crack, or thin deposit in this area requires careful review.
Void At The Center Of A High-Aspect-Ratio Hole
Deep, narrow holes are harder to clean and plate uniformly. If the center also has the lowest copper thickness, a void there may combine two weaknesses.
The PCB aspect ratio should therefore form part of the defect investigation.
Void In A Filled Or Capped Via
Copper-filled structures use different acceptance characteristics, including fill quality, internal seams, voids, dimples, cap thickness, and wrap plating.
Consequently, inspectors should first identify the PCB via type before applying acceptance criteria.
Why Can PCB Plating Voids Pass Electrical Testing?
Electrical testing checks whether the tested network currently has continuity and whether isolated networks remain separate. It does not measure the complete geometry of every hole wall.
A partially plated hole may still pass because:
- Copper remains on part of the circumference
- Parallel vias connect the same layers
- Redundant ground or power connections mask the defect
- Test current remains too low to stress the weak area
- The defect has not opened at room temperature
- Probes do not isolate one individual via
- Thermal expansion has not yet enlarged the defect
Therefore:
Electrical Test Passed ≠ Hole-Wall Structure Verified
A weak barrel can conduct during final PCB inspection but fail after reflow, wave soldering, repair, thermal cycling, or field operation.
Electrical testing still provides valuable evidence. However, it cannot replace a representative PCB microsection when the concern involves plating continuity, thickness, cracks, or internal-layer interfaces.
How Should PCB Plating Voids Be Measured?
A useful report should describe the void in both directions.
Longitudinal Extent
This measurement describes how far the void extends through the board thickness.
The report should state:
- Start and end positions
- Distance from the nearest outer surface
- Proximity to internal-layer connections
- Percentage of board thickness, when required
- Whether the void crosses a layer interface
Circumferential Extent
This measurement describes how far the void extends around the barrel circumference.
One two-dimensional microsection does not show the entire circumference. Therefore, an inspector may need:
- Parallel sections
- Additional holes
- Sequential grinding
- Another coupon
- Destructive analysis of an affected production board
Number And Distribution
One isolated void creates a different process signal from repeated voids in similar panel positions.
The report should identify:
- Number of affected holes
- Hole diameters
- Via functions
- Panel positions
- Board locations
- Whether defects align at the same depth
- Whether one or both barrel sides show voids
An average value alone cannot describe these conditions.
Can Microsection Preparation Create A False Defect?
Yes. Poor specimen preparation can create scratches, copper smearing, edge rounding, pull-out, staining, or an off-center section.
These artifacts may hide copper or imitate a void.
A reliable microsection process should control:
- Coupon selection
- Hole-center alignment
- Mounting
- Grinding
- Polishing
- Etching
- Lighting
- Magnification
- Image calibration
- Operator interpretation
The IPC-TM-650 microsection method requires proper preparation so inspectors do not smear one material over another or round the metal surfaces under evaluation. Its public microsection preparation method also emphasizes grinding the target PTH to the specified position.
If the observed void appears only on one side of one section, the supplier should confirm that the section passes through the relevant hole region. Otherwise, the image may not represent the defect’s true size.
What Causes PCB Plating Voids?
PCB Plating Voids usually indicate a breakdown in hole preparation, initial metallization, adhesion, or plating-process control.
| Possible Cause | Mechanism | Evidence To Review |
|---|---|---|
| Drill Debris | Material blocks part of the hole wall | Drill quality and cleaning records |
| Inadequate Desmear | Resin remains over exposed copper or dielectric | Desmear parameters and microsection |
| Excessive Desmear | Hole wall becomes damaged or chemically unsuitable | Bath control and material compatibility |
| Rough Hole Wall | Fibers, gouges, or debris interrupt coverage | Drill condition and entry/backup material |
| Contamination | Oil, particles, or chemistry residue prevents deposition | Rinse control and bath analysis |
| Electroless Copper Skip | Initial conductive layer remains incomplete | Metallization checks |
| Poor Plating Contact | Panel receives unstable current | Clamp and contact inspection |
| Low Solution Exchange | Chemistry does not reach deep hole regions adequately | Agitation and hole aspect ratio |
| Bath Chemistry Excursion | Additives or contaminants leave the operating window | Chemical-analysis records |
| Particle Entrapment | A particle blocks deposition and later detaches | Filtration and cleanliness data |
| Uneven Copper Distribution | Local current distribution becomes difficult | Copper-density map |
| Handling Damage | Copper separates or scratches after deposition | Process-stage comparison |
IPC’s PCB-fabrication training material treats plating voids, wedge voids, inadequate desmear, hole-wall pull-away, adhesion loss, and interconnect defects as separate conditions. Therefore, a root-cause report should not use “plating problem” as the complete explanation.
The previous PCB plating uniformity analysis can help determine whether the defect follows a predictable panel or hole-geometry pattern.
Can Finished Hole Size Reveal Plating Voids?
Not reliably.
Finished hole size can help identify excessive or insufficient overall buildup. However, a localized void may occupy only part of the barrel while the measured diameter still meets tolerance.
Furthermore, finished diameter depends on:
- Drill size
- Drill wear
- Hole-wall preparation
- Electroless copper
- Electrolytic copper
- Final surface finish
- Measurement method
- Local nodules or roughness
Therefore, the PCB drill size vs finished hole size relationship supports the investigation but cannot prove complete plating coverage.
What Reliability Problems Can PCB Plating Voids Cause?
The dielectric expands more than the copper barrel in the board’s thickness direction during heating. As a result, soldering and thermal cycling place mechanical stress on plated holes.
A void can reduce the copper area available to carry current and withstand that stress.
Possible consequences include:
- Increased local current density
- Local heating
- Progressive barrel cracking
- Intermittent connections
- Inner-layer separation
- Open circuits after thermal cycling
- Reduced repair tolerance
- Early field failure
The risk rises when the design combines a void with:
- Thin remaining copper
- High aspect ratio
- Thick PCB construction
- High-temperature assembly
- Multiple soldering cycles
- Repeated component rework
- High operating current
- Large temperature changes
- High-reliability service conditions
Plating voids can also appear beside material damage. However, inspectors should evaluate PCB delamination separately because it follows different dimensional and location criteria.
What Should A Supplier Do After Finding PCB Plating Voids?
The supplier should not immediately sort the lot using electrical testing alone.
A useful containment process includes:
- Hold the affected production lot.
- Record the affected panel, board, hole, and coupon positions.
- Confirm the microsection preparation quality.
- Prepare additional sections from representative locations.
- Compare different plating loads or production flights.
- Review drill, desmear, metallization, bath, filtration, and contact records.
- Determine whether the defect follows a panel-position pattern.
- Assess shipped or work-in-process lots produced under the same conditions.
- Implement and verify the corrective action.
- Document the final disposition against the governing requirement.
If finished assemblies already exist, the investigation may also need:
- X-ray inspection
- Continuity or resistance measurements
- Thermal stressing
- Destructive analysis
- Cross-sectioning
- Review of reflow and repair history
A structured PCBA failure analysis should separate the original fabrication defect from damage introduced during assembly or rework.
What Evidence Should Buyers Request?
A plating-void report should include:
- PCB part number and revision
- Lot and date code
- Production panel identification
- Plating flight or batch
- Applicable IPC specification and revision
- Product class
- Customer drawing requirement
- Original microsection images
- Calibrated scale and magnification
- Void dimensions
- Hole diameter and board thickness
- Void location relative to internal layers
- Minimum remaining copper thickness
- Number of affected holes and panels
- Coupon-to-production-board correlation
- Electrical test result
- Root-cause evidence
- Containment scope
- Corrective-action verification
The buyer should reject a report that shows only one cropped image without the board location, measurement scale, specification reference, or lot scope.
During PCBA first article inspection, high-risk projects should preserve the original coupon images and measurement records as a baseline for later lot comparisons.
Recommended PCB Plating Voids Drawing Note
A fabrication drawing may state:
Evaluate copper plating voids to the specified IPC-6012 performance class and applicable IPC-A-600 revision. Report any void at an internal-layer interface, any condition that reduces copper below the specified minimum, and any repeated void pattern found during coupon or production-board inspection. Provide calibrated microsection images, individual measurements, panel location, and lot traceability.
For higher-reliability products, the buyer may add:
Do not accept plating voids without written customer disposition, regardless of electrical test result.
However, stricter requirements can increase inspection, coupon, microsection, and scrap costs. Therefore, the buyer should connect the requirement to the actual reliability risk rather than applying it automatically to every commercial PCB.
What Does Haode Need To Review PCB Plating Voids?
Provide:
- Gerber, ODB++, or IPC-2581 data
- Fabrication drawing
- Approved stackup
- Drill and tool tables
- Finished hole requirements
- Board thickness
- Copper thickness requirements
- Via types
- Product classification
- Applicable IPC revisions
- Microsection images
- Panel and coupon layout
- Electrical test records
- Lot and plating-batch information
- Assembly thermal history
- End-use environment
These files allow Haode to determine whether the defect affects a critical connection, whether the coupon represents the PCB, and whether additional inspection can support a defensible disposition.
The PCB DFM checklist should define these requirements before production instead of waiting for a disputed microsection result.
PCB Plating Voids Acceptance Checklist
Before accepting an affected lot, confirm:
- Did the inspector identify the defect correctly?
- Does the microsection show the hole center accurately?
- Does the report measure longitudinal and circumferential extent?
- Is the void near an internal-layer connection?
- Does remaining copper meet the minimum?
- Are opposite or aligned voids present?
- Does the coupon represent the production feature?
- Did other panels show the same pattern?
- Does the disposition cite the exact standard and revision?
- Did electrical testing mask a redundant connection?
- Has the supplier identified the process cause?
- Has the supplier verified corrective action?
The practical acceptance rule is:
Accept a plating void only when the governing specification expressly permits its measured condition and the remaining structure meets every copper, connection, and reliability requirement.
If the supplier cannot demonstrate those points, the buyer should hold the lot rather than relying on electrical continuity alone.
